Category Archives: Announcements

Shapeoko: Part 1

My Shapeoko kit arrived from Inventables while I was away at SC.

I’ve been trying to build myself a small CNC milling machine since 2009, and contemplating it for longer than that. It became clear that my original design, however educational, was a dead end sometime last year. I’d been idly watching the Shapeoko project for some time as it had similar aspirations to my design, and a couple months ago I was in a particularly mechanical mood when I saw that a batch had reached enough buyers to be produced, so I bought in for a mechanical kit to mount my existing electronics on.

The Shapeoko community is really excellent, and the kit was designed to be flexible, so I’m starting off with some suggested modifications – I’m using NEMA23 motors instead of the usual NEMA17 on the X and Y axis, because I already had some nice Lin Engineering 130 oz-in NEMA23 motors and the frame can fit them. I’m configuring for dual Y motors, which give more even force across the Y axis, and routing my belts on the outside of the frame, since I needed to buy different hardware for the NEMA23 motors anyway and this particular modification is widely recommended.

There is a gallery to document my first round of assembly below the fold (captions don’t display properly in the RSS feed).
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SC12

I will be at SC12 November 10-16, with the Aggregate.org/University of Kentucky exhibit in booth 631.

I will be posting pictures and impressions through at least one of my online presence mechanisms . I fully expect it to be weird this year with a bunch of the national labs pulled out due to travel restrictions, but it should be interesting.

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Touchpad

I picked up one of the $150 refurbished 32GB Touchpads in the last firesale on Sunday. It seems like HP has done their very best to get as many Touchpads into the hands of hackers as possible, so whether or not it is well supported by HP, the community will do something fun with it. Besides, a $150 ARM developement platform that will boot Android, various Linux chroots, AND let me play with WebOS was too appealing to pass up.
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SC’11 Lessons

I learned some really interesting things at SC this year, and now that I’ve had a day to process, I want to share. Many of these observations come from first or second hand conversations, or justifiable interpretations of press releases, so I don’t promise they are correct, but they are plausible, explanatory, and interesting. I apologize for the 1,000 word wall of text, but there is a lot of good stuff.

  • This is the big one: I’m pretty sure I understand the current long term architecture plan being pursued by Intel, AMD, and Nvidia. This plan signals the end of the current style of monolithic symmetric processor cores.
    They are all apparently pursuing designs with a small N of large integer units, coupled to M >> N SIMD engines.

    • Nvidia’s “Project Denver” is a successor/big sibling to Tegra design, and appears to be the beginning of a line with 2-8 64-bit (probably) ARM cores tightly integrated with a big honking GPU-like SIMD structure for FP. The stale press release about this stuff is kind of nauseating to read, but it looks like they’re betting the farm on that design.
    • Intel’s HPC efforts are going to be based on a lot of MIC (Many Integrated Cores, successor to the Larabee stuff) parts coupled with a few big cores like the current Xeons. The MIC chips are basically large numbers of super-Atoms: tiny, simple, dumb integer units attached to big SWAR (SIMD Within a Register) units focused on SSE/AVX performance. This is less speculative than most observations, they made a pretty good press push (This for example) on this idea.
      The ring interconnects and higher per-“thread” hardware complexity are probably not a good idea in the long run (IMHO), but having an integer unit for every big SWAR engine will be a major advantage in terms of programming environment and code generation. I suspect the more cautious approach is because Intel doesn’t want/can’t afford another Itanic, where the tools couldn’t generate good code for the programming model on their intended high-end part.
    • AMD’s two current products are stepping stones to a design similar to Nvida’s – Bulldozer is a design with some ridiculously powerful x86-64 integer units decoupled from a smaller number of shared FPUs. The APU (I haven’t heard the “Fusion” name in a while) designs are CPUs tightly coupled to GPU structures. The successor parts will be a hybrid of the two – a few big, bulldozer style integer units, with a large number wide next-gen GPU SIMD structures coupled to them.

    I think this is generally a good design direction, particularly with current directions in computing in mind, but it is going to make the compiler/concurrent programming world exciting for a while.

  • AMD appears to be gearing up to abandon a fifth generation of GPGPU products. CTM, CAL, Brook+, OpenCL on 4000 series cards have all been deprecated while still shipping, and indications are that OpenCL (and general driver) support for the current architecture (4-wide VLIW SIMDs, like in the 5- and 6- series) has been relegated to second-class citizen status, while they work on a next generation architecture. The rumor is the next gen parts will be 4 independent banks of SIMD engines instead of 4-wide VLIW SIMD engines, which should be both both nicer to program and generate code for and more similar to Nvidia.
  • Nvidia is going to open source their CUDA environment. One of the primary objections to CUDA in a lot of circles is reluctance to use a proprietary single-vendor programming environment (people who have been in super/scientific computing for long have all been burnt on that in the past), and the Integer+SIMD model is going to require that not be an issue. This is assembled from information from several places, including PGI, Nvidia, and various scientific compute facilities, much of it second hand or further, but it would make sense.
  • I still don’t exactly know what went down at Infiscale, but the impression that the Perceus community was abandoned by the company, the developers fled, and it was a bad scene seems to be correct. No one I know that was there seems to be talking, but they’re all on their way to other interesting things, especially Greg Kurtzer’s Warewulf3 project at LBL.
  • The dedicated high performance compute nodes in Amazon’s EC2 cloud are actually connected as a few large partitionable clusters, users just can’t (nominally, don’t need to) see and instrument the topology like they could with a normal cluster. This is from interpreting press releases, because the people manning Amazon’s booth really didn’t want to chat (and, in fact, were kind of dicks when we tried). This explains how they’ve been getting performance out of a loosely coupled cloud — which is to say they aren’t, they just have a huge cluster attached to their cloud that shares the interface.
  • The current hard drive production problems have given SSDs the opportunity they need to become first class citizens. Talking to OEMs, the wholesale cost per capacity on HDDs almost tripled, and the supply lines aren’t all that stable, so everyone is scrambling to make things work with mostly SSDs. I saw a lot of interesting new form factors for SSDs, and several flavors flash or battery backed “nonvolatile” DRAM floating about as well, so the nature of storing data-sets is changing.
  • I saw motherboards with 32 DIMM slots (mostly AMD Interlagos based) on the floor. I saw 32GB DIMMs on the floor. I saw some shared-memory systems with multiple Terabytes of RAM in them. The standard for high memory machines has roughly quadrupled in the last year or two.
  • The number of women (not booth babes, real technical people, especially younger ones) and educators on the show floor this year was way higher than in the past. This is very good for the field.

I think that covers most of the really good stuff coming off the floor this year, although I am still processing and may come up with some other insights when I’ve had more sleep and discussion.
Also, Pictures! WOO! (Still sorting and uploading the last batch at time of posting).

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Headed out to SC11 in Seattle, WA. for the week. Technical interest, travel complaints, booth hacks, advertising mockery, and schwag to follow.

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Google Plus

I’ve been playing with Google+ for the last couple days, and am finding it pretty interesting. To share some observations that will be tedious to anyone not interested in plus, UI design, and such geekery:
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Google Plus?

Google is trying again with social networking with Google Plus. It actually looks pretty interesting; the group management (“cirlces”) looks reasonable, the platform-independent n-party text/voice/video chat (“hangouts”) looks spectacular, and the interest grouping (“sparks”) would make a good standalone feature. I’m going to wait and see before I deal with it, but the “Google already knows all there is to know about me” reality gives it a leg up on the competition, and if they rigged it together with standard technology (they way Google talk is a good Jabber/XMPP implementation with some extensions turned on) I might at least peer some of my “on the real god damn internet” identity into it like I do with Buzz.

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Congratulations Tom and Cristina


A little belated because I didn’t get to plugging my camera in to a computer until today, but congratulations are in order for my housemates Tom and Cristina, who got married last Saturday in an incredibly well suited lighthearted ceremony. Best of luck guys!

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Research Updates / LLVM Is a PITA

I’ve spent the last several months discovering ways in which LLVM is excessive, ill-behaved, oversold, broken or simply lying in it’s documentation while working on my master’s project. In fact, that is almost ALL of what I accomplished in the past several months, and it was griding on me psychologically. Last weekend, I finally admitted to myself that, for a mixture of psychological and technological reasons, I wasn’t going to be able to finish the project using LLVM. I’ve always had a bail-out path set up to do a simpler full-custom compiler if something proved intractable, and Monday I talked to the advisor about putting that plan into action.

I’m now building a simple C-like language with PCCTS (old school 1.33MR33 emits-pure-C ANTLR and SOURCERER PCCTS, not modern ANTLR), hand-coding C for the remainder, and concentrating on the technically interesting matters. To that end, I’ve accomplished more conceptual work in the last week than the two preceding months, started laying out my new tools, and feel much better. The best “aha” moment I’ve had in months came when I sat down and worked out how the stack and calling conventions were going to work in my new system; LARs are beautiful and well-suited to real world problems in a whole host of ways I didn’t understand before.

Note that I don’t think LLVM is entirely bad; in conception, having a nice cleanly-interfaced compiler infrastructure with a library of frontends, backends, optimizer passes and other common components which snap together via clean interfaces, high level specifications, and a standardized intermediate representation is exactly how compiler tools should be structured. The problem is that LLVM has been drastically oversold, and overcomplicated. Every neat-looking interface has a mess of poorly-documented C++ that needs to be written to support it. Everything is set up with an emphasis on LLVM’s JIT/VM features, making it unnecessarily clumsy to use to produce pure compilers, or interface with external tools. Worst of all, the documentation is deceiving — much worse than incomplete, it appears complete, but is frequently deceptive or wrong. To pick one of the more egregious examples, much of the document points to the MIPS fronted as an example. This should be a good thing – MIPS is a simple design familiar to almost anyone in computing, but the MIPS backend is broken, in apparently fairly fundamental ways. The register descriptions are buggy in ways which cause it to generate incorrect code for any input containing floats, and it appears to be a high-level design problem descended from naively trusting that the register description and allocation mechanisms work as described. It is probably already a good tool for writing production compilers for established designs, but it really isn’t suited to writing research compilers.

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Blog Move

This blog is in the process of moving in from it’s previous location at http://www.engr.uky.edu/~pseber0/ to it’s new home at pappp.net on bluehost. This current page will no doubt be repeatedly created and destroyed in the process, as I try to explain to the terrible migration tool about internal linking, resources, categories, and a variety of other things it is doing it’s best to lose or mangle. Things should be up and running in a couple of days, when the links will be updated, and the relocation notice will go up at the old location. This post also has a full set of categories, to force updates.

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