Hate Verilog? Detest VHDL? You’re not the only one. Xilinx rolls out easier-to-use free FPGA programming tools after developer outcry

Article note: High-level programming FPGAs never really pans out. Reliably synthesizing arbitrary structures HDLs is hard and unpredictable enough, higher level not-designed-to-force-you-to-think-about-hardware languages ends up being intractable or random behavior. I suspect this will realistically be restricted to stringing together IP cores with some options - but I also suspect that's more-than-fine with Xilinx.