Source: The Register
Article note: High-level programming FPGAs never really pans out.
Reliably synthesizing arbitrary structures HDLs is hard and unpredictable enough, higher level not-designed-to-force-you-to-think-about-hardware languages ends up being intractable or random behavior.
I suspect this will realistically be restricted to stringing together IP cores with some options - but I also suspect that's more-than-fine with Xilinx.
Vitis toolkit for the rest of us, coming soon, allegedly
If you hate writing Verilog, VHDL, and other hardware design languages, used to craft computer chips and configure FPGAs, you're far from the only one.…
