RISC-V: The Last ISA?

Article note: I went to the RISC-V BoF at SC22 this week and ... lost most of my interest in RISC-V. Aside from the unusual vector extension style they chose being ...likely not an effective choice for efficiently extracting parallelism... quite some time ago now, the big problem I (and apparently half the room there) see coming is the _enormous_ enthusiasm for a combinitoric explosion of bespoke ISA extensions with no coherent plan for compiler and library support. If every RISC-V "HPC" feature is gated behind some mutually-exclusive bullshit proprietary LLVM fork or spray of pragmas, no one is going to use them, because the compiler and library writers won't use them, and all software will be compiled against the not-very-inspiring base profile, making it more-or-less interchangeable with any other general purpose CPU design, but less mature.