CISC-y RISC-ness

Article note: This is written through a _super_ warped lens, possibly the lensing effects of David Patterson's ego. Article talks about VLIWs as "The Next RISC" without Josh Fisher's Trace Scheduling and MultiFlow, or Apollo's Prism or Cydrome or...basically anything that happened in the 80s. It doesn't even mention the dead elephant in the room, Itanium (yeah yeah, Intel liked "EPIC" to describe their even longer words, it's still a static VLIW, and it still didn't really work). It also avoids comparisons to the "modern" (...starting with the Nexgen NX586->AMD K6 and Intel P6 designs from around the time Transmeta was founded in '95) superscalar multiple-issue out-of-order dynamic-JIT-in-hardware type designs that largely beat firmware code-morphing (and everything else) out because even though they worked on a small peephole of instructions with dumb heuristics, they could do dynamic shit to keep the pipeline full. Plus, I now object to anyone who acts like RISC-V is "one" instruction set, it's a pile of disjoint extensions, many of which implement ideas which were neither new nor good at the time they were bolted on.