Source: OSNews
Built on a 2 nanometer technology node, the processor’s design will contain 11 high-performance cores operating at more than 5.7 GHz, AI inference accelerators for in-transaction fraud detection, a dedicated on-chip data processing unit for I/O acceleration, and a large cache architecture for demanding enterprise workloads. The chip is architected to not contain separate Arm and IBM cores: each processor core can natively execute Arm and IBM Z, or Arm and LinuxONE, instructions concurrently while prioritizing the platform’s established performance, security, encryption, and availability characteristics. IBM Z and LinuxONE platforms are capable of scaling to hundreds of cores and tens of terabytes of memory.
↫ IBM press release
IBM is still doing some amazing chip architecture design. ServeTheHome has more details of how this works:
A key choice here is that IBM implemented AArch64 in full hardware rather than through translation. This design uses a little-endian Arm implementation alongside big-endian z/Architecture, with AArch64 v9.3, SVE and SVE2 support, and 2,792 implemented AArch64 instructions. IBM also claims Arm SystemReady compliance, which matters for how much off-the-shelf Arm software this core can absorb. This is absolutely crazy technology. Arm software sees a native Arm processor. Arm runs unmodified, out-of-the-box, and onto a standard Arm platform. IBM said the 2792 AArch64 instructions are more than twice the Z instructions. IBM made a funny quip about “reduced” in RISC.
↫ Patrick Kennedy at ServeTheHome
This is bonkers technology. We can only dream of this ever serving a home.
