Monthly Archives: March 2022

Article note: Duh? Any automated optimizer can, intentionally or otherwise, have its reward function set to do undesirable things.

Article note: Oh that's cool. Their VGA-via-PIO alone setup is a good trick.

Article note: This is a lovely historically-situated intro to modern assembly (Other than the two's compliment error).

Enlarge (credit: saccade.com)

The history of computing could arguably be divided into three eras: that of mainframes, minicomputers, and microcomputers. Minicomputers provided an important bridge between the first mainframes and the ubiquitous micros of today. This is the story of the PDP-11, the most influential and successful minicomputer ever.

In their moment, minicomputers were used in a variety of applications. They served as communications controllers, instrument controllers, large system pre-processors, desk calculators, and real-time data acquisition handlers. But they also laid the foundation for significant hardware architecture advances and contributed greatly to modern operating systems, programming languages, and interactive computing as we know them today.

In today’s world of computing, in which every computer runs some variant of Windows, Mac, or Linux, it’s hard to distinguish between the CPUs underneath the operating system. But there was a time when differences in CPU architecture were a big deal. The PDP-11 helps explain why that was the case.

Article note: What is it with the aggressive opposition to public health measures largely identical to those we've had for decades? This basically says "we have to assume everyone is an unvaccinated moron forever."

Article note: It's sort of shocking how much of a hard problem generalized parametric CAD is, both in the algorithmic and user perspective. The SolveSpace+Blender arrangement here actually seems reasonably pleasant. Also, from the comments, I didn't realize the commercial offerings were almost all front-ends to the same set of kernels, D-Cubed 2D DCM for 2D constraint solving, and either Parasolid or ACIS (or, for Autodesk, a fork of an old version of ACIS) for the geometric kernel. A couple of the small and/or open source players are using different parts, but the big players are basically hyper-specialized chrome.

Article note: Ooh, timely, I got curious about those things the other day. Not high on my list of needs, but nice to know they're both quite usable and as sketchy as they seem.

Article note: Aw, User Friendly was a classic of early internet culture. At least it's archived.

Article note: That is _really_ cool and market changing. Most of the relevant industry players onboard with the same spec, and they're agreeing to a complete physical and protocol interconnect standard, so you'll be able to combine chiplets the way we do AXI or Wishbone in hardware description languages, or composing chips on standard busses. Should be some interesting mix-and-match, and opportunities for small players to pop in with insurgent co-processor designs and such.

Enlarge / A sample chiplet design, with the CPU dies made with a more advanced manufacturing process and the chipset and some other functions made on older, cheaper processes. (credit: Universal Chipset Interconnect Express)

Some of the CPU industry's heaviest hitters—including Intel, AMD, Qualcomm, Arm, TSMC, and Samsung—are banding together to define a new standard for chiplet-based processor designs. Dubbed Universal Chiplet Interconnect Express (UCIe for short), the new standard seeks to define an open, interoperable standard for combining multiple silicon dies (or chiplets) into a single package.

Intel, AMD, and others are already designing or selling chiplet-based processors in some form—most of AMD's Ryzen CPUs use chiplets, and Intel's upcoming Sapphire Rapids Xeon processors will, too. But these chips all use different interconnects to enable communication between chiplets. The UCIe standard, if it succeeds, will replace those with a single standard, in theory making it much easier for smaller companies to take advantage of chiplet-based designs or for one company to include another company's silicon in its own products.

• 

  The UCIe (which is the name of the specification and the organization) lays out its goals in defining the UCIe standard. [credit: Universal Chipset Interconnect Express ]

Chiplet-based designs are advantageous when making large chips on cutting-edge manufacturing nodes partly because they cut down on the amount of silicon manufacturers need to throw out. If a manufacturing defect affects one CPU core, tossing (or binning) a single 8-core chiplet is a whole lot cheaper than having to toss a huge 16- or 32-core processor die. Chiplet designs also let you mix-and-match chips and manufacturing processes. You could, for example, use an older, cheaper process for your chipset and a newer, cutting-edge process for your processor cores and cache. Or you could put an AMD GPU on the same package as an Intel CPU.