{"id":152,"date":"2009-09-10T00:20:06","date_gmt":"2009-09-10T04:20:06","guid":{"rendered":""},"modified":"2011-02-02T00:28:18","modified_gmt":"2011-02-02T05:28:18","slug":"hdl-testbenches","status":"publish","type":"post","link":"https:\/\/pappp.net\/?p=152","title":{"rendered":"HDL Testbenches"},"content":{"rendered":"\n<p>After three classes (EE281, EE480, EE585) where I should have been taught how to write real, procedural testbenches for my digital circuit simulation instead of clicking in inputs on <a class=\"externlink\" title=\"Go to http:\/\/www.xilinx.com\/tools\/logic.htm\" href=\"http:\/\/www.xilinx.com\/tools\/logic.htm\">ISE<\/a>&#8217;s (ISE is the subject of much swearing and hatred) waveform editor, there was a nominal effort to demonstrate it in EE685, and between that example and the <a class=\"externlink\" title=\"Go to http:\/\/www.amazon.com\/Verilog-HDL-Digital-Design-Modeling\/dp\/1420051547\" href=\"http:\/\/www.amazon.com\/Verilog-HDL-Digital-Design-Modeling\/dp\/1420051547\">Verilog book<\/a> I bought for my own edification some time ago (It&#8217;s an OK book: I&#8217;m yet to find a HDL text I really like), I finally managed to get it down.  This is important for three reasons: First: NO MORE CLICKING! I can write little procedural blocks to generate counting-order covering inputs, or other arbitrary stimulus.  Second: Automatic Testing! For simple modules, I can simply write two logically equivalent but stylistically different versions, and, barring any design-level fuckups, determine that they both work by telling the simulator to compare the two version&#8217;s behavior and alert me if they differ.  Third (and most signifigantly) it allows me to do my check\/test\/verify my modules without dealing with ISE.  There are a number of free Verilog tools, most significantly <a class=\"externlink\" title=\"Go to http:\/\/www.icarus.com\/eda\/verilog\/\" href=\"http:\/\/www.icarus.com\/eda\/verilog\/\">Icarus Verilog<\/a>, a Free (GPL) synthesis\/simulation suite which seems to be well liked (and builds and installs easily on my machine), which allow me to have a whole toolchain without the hassle of maintaining my own ISE installation, or putting up with the glacially slow (despite being very, very powerful; bad configuration) lab machines for longer than is required to generate a test run to turn in for class.<br \/>\nIcarus looks to be an interesting challenge; it definitely doesn&#8217;t go out of it&#8217;s way to be user friendly, it requires an external tool like <a class=\"externlink\" title=\"Go to http:\/\/gtkwave.sourceforge.net\/\" href=\"http:\/\/gtkwave.sourceforge.net\/\">GTKWave<\/a> to display waveforms, and it&#8217;s got some features and switches that I&#8217;m not even sure what are for, but it is <a class=\"externlink\" title=\"Go to http:\/\/iverilog.wikia.com\/wiki\/Main_Page\" href=\"http:\/\/iverilog.wikia.com\/wiki\/Main_Page\">documented<\/a> and seems to be quite reasonable.<br \/>\nOne feature Icarus doesn&#8217;t (AFIK) have is the ability to synthesize to the various <a class=\"externlink\" title=\"Go to http:\/\/en.wikipedia.org\/wiki\/Programmable_logic_device\" href=\"http:\/\/en.wikipedia.org\/wiki\/Programmable_logic_device\">programmable chips<\/a> (which are all very, very proprietary).  I do have my <a class=\"externlink\" title=\"Go to http:\/\/www.digilentinc.com\/Products\/Detail.cfm?Prod=S3BOARD\" href=\"http:\/\/www.digilentinc.com\/Products\/Detail.cfm?Prod=S3BOARD\">own FPGA board<\/a>, which I got in a burst of excitement after first being exposed to FPGAs, and have never had a chance to play with as much as I&#8217;d like.  Somewhere deep, deep down on the list of projects is to get a decent programming cable for it (my current one is an old parallel model), and spend some quality time playing around with it, I clearly <a class=\"externlink\" title=\"Go to http:\/\/www.fpga4fun.com\/\" href=\"http:\/\/www.fpga4fun.com\/\">wouldn&#8217;t be alone<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>After three classes (EE281, EE480, EE585) where I should have been taught how to write real, procedural testbenches for my digital circuit simulation instead of clicking in inputs on ISE&#8217;s (ISE is the subject of much swearing and hatred) waveform &hellip; <a href=\"https:\/\/pappp.net\/?p=152\">Continue reading <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[4,8,37,1,12],"tags":[],"class_list":["post-152","post","type-post","status-publish","format-standard","hentry","category-computers","category-diy","category-electronics","category-general","category-oldblog"],"_links":{"self":[{"href":"https:\/\/pappp.net\/index.php?rest_route=\/wp\/v2\/posts\/152","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pappp.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/pappp.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/pappp.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/pappp.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=152"}],"version-history":[{"count":0,"href":"https:\/\/pappp.net\/index.php?rest_route=\/wp\/v2\/posts\/152\/revisions"}],"wp:attachment":[{"href":"https:\/\/pappp.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=152"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/pappp.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=152"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/pappp.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=152"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}