{"id":109310,"date":"2026-08-27T10:30:41","date_gmt":"2026-08-27T14:30:41","guid":{"rendered":"http:\/\/pappp.net\/?guid=147f2ebd0fa6bc23d00d535580c362ef"},"modified":"2026-08-27T10:30:41","modified_gmt":"2026-08-27T14:30:41","slug":"ibm-announces-dual-isa-processor-arm-and-ibm-z-code-running-natively-on-the-same-cores","status":"publish","type":"post","link":"https:\/\/pappp.net\/?p=109310","title":{"rendered":"IBM announces dual-ISA processor: ARM and IBM Z code running natively on the same cores"},"content":{"rendered":"

Source: OSNews<\/a><\/p>\n

Article note: This is very IBM. \nDual-architecture parts with insane memory corner-turning hardware to keep them consistent, like they were doing with BlueGene Power CPU+Nvidia GPU on single memory machines a decade or two ago. \nKind of weird that it's AArch64 and now Power since the Z and big Power lines already share a lot of functional units, but Arm is obviously the bigger platform at this point. \nAnd, of course, you can still run Cobol-on-MVS jobs that were written in the 70 as though it were native.<\/div>
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Built on a 2 nanometer technology node, the processor’s design will contain 11 high-performance cores operating at more than 5.7 GHz, AI inference accelerators for in-transaction fraud detection, a dedicated on-chip data processing unit for I\/O acceleration, and a large cache architecture for demanding enterprise workloads. The chip is architected to not contain separate Arm and IBM cores: each processor core can natively execute Arm and IBM Z, or Arm and LinuxONE, instructions concurrently while prioritizing the platform’s established performance, security, encryption, and availability characteristics. IBM Z and LinuxONE platforms are capable of scaling to hundreds of cores and tens of terabytes of memory.<\/p>\n↫ IBM press release<\/a><\/cite><\/blockquote>\n\n\n\n

IBM is still doing some amazing chip architecture design. ServeTheHome has more details of how this works:<\/p>\n\n\n\n

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A key choice here is that IBM implemented AArch64 in full hardware rather than through translation. This design uses a little-endian Arm implementation alongside big-endian z\/Architecture, with AArch64 v9.3, SVE and SVE2 support, and 2,792 implemented AArch64 instructions. IBM also claims Arm SystemReady compliance, which matters for how much off-the-shelf Arm software this core can absorb. This is absolutely crazy technology. Arm software sees a native Arm processor. Arm runs unmodified, out-of-the-box, and onto a standard Arm platform. IBM said the 2792 AArch64 instructions are more than twice the Z instructions. IBM made a funny quip about “reduced” in RISC.<\/p>\n↫ Patrick Kennedy at ServeTheHome<\/a><\/cite><\/blockquote>\n\n\n\n

This is bonkers technology. We can only dream of this ever serving a home.<\/p>","protected":false},"excerpt":{"rendered":"

Built on a 2 nanometer technology node, the processor\u2019s design will contain 11 high-performance co…<\/p>\n

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